1. Field of the Invention
The present invention relates to memory testing, and more specifically to efficiently testing and reporting failed memory locations as well as to efficiently allocating redundant resources to repair defective memory locations.
2. Description of the Related Art
One of the first steps in memory repairing is to determine failed memory locations, usually by writing data to an array of memory locations, reading data from those memory locations, and then comparing the read data to the data previously written to determine failed memory locations.
Memory testing has involved using an external memory tester with direct access to the memory's control, address and data pins. As the memory is tested, the row address, column address and the failed I/O position of each failed memory location are stored in the external memory tester for redundancy repair analysis. Typically the results of the analysis are used by a fusing cutting machine to determine which fuses to cut or anti-fuses to connect. Direct access memory testing is done at the external memory testing speed, which can be many times slower than the intended memory operating speed. As a result, it may not be possible to detect memory failures occurring at the memory operating speed. In addition, in direct access memory testing, all memory pins must be routed back to the chip pads to be directly accessed by the external memory tester. For many designs, this routing is not feasible.
Another memory testing approach is built-in self-test (BIST), which embeds parts of the testing circuitry in the memory to be tested, instead of solely depending on the external memory tester. The BIST executes a set of algorithmic verification tests directly on the memory array. Conventionally, the BIST receives clock signals and test data from the external memory tester, and reports failed memory locations to the external memory tester for redundancy repair analysis. The BIST typically runs at the external memory tester frequency, which can be substantially lower than the memory operating frequency. As a result, memory failures occurring at the memory operating frequency still are not detectable. Another BIST shortcoming has been the latency of data transmission between the BIST and the external memory tester. For a memory with row and column failures, the BIST reports as many as 512 failures per test set for each row failure, and similarly for column failures. Consequently, thousands of failed memory locations may be reported, even though many or most of them are redundant. In addition, the narrow data path from the BIST to the external memory tester requires many tester clock cycles to transfer information for just one failed memory location. Thus, the testing time, i.e., thousands of failed memory locations multiplied by the number of clock cycles to transfer information for one failed memory location, becomes relatively substantial.
It would be advantageous to provide a method and system for more efficient testing and reporting of failed memory locations.